Integrated circuits are formed by patterning successive layers on a substrate such as a silicon wafer. Each of the successive circuit layers is typically patterned using a lithography process. In a lithography process, light (or massive particles, such as ions or electrons) interacts with a mask that includes a pattern to be transferred to a substrate. Radiation then transfers the mask pattern to the surface of a substrate.
One concern in a lithography process is that the layer design layout be accurately reproduced on the surface of the substrate. However, the optical characteristics of the lithography system may not reproduce the design layout with adequate fidelity. For example, an optical projection system including lenses is typically positioned between the mask and substrate. The lens system may act as a low band-pass filter, so that some information carried by the radiation may not reach the substrate. Because some information being carried by the radiation may be lost, features patterned on the substrate may differ from the corresponding mask feature.
One method that may be used to more accurately reproduce the intended design on the substrate is to include additional features on the mask, such as optical proximity correction (OPC) features. FIGS. 1A to 1D illustrate an example of an OPC feature that may be used to increase pattern fidelity. FIG. 1A shows a T-shaped mask feature with dimensions near the resolution limit of a projection lens of a lithography system. FIG. 1B shows that the feature of FIG. 1A as transferred to the surface of a substrate is significantly distorted due to rounding of the corners. FIG. 1C shows the mask feature with added OPC serifs. FIG. 1D illustrates that the rounding is improved due to the inclusion of OPC serifs on the mask.
For each layer layout of a particular integrated circuit or combination of integrated circuits, circuit designers apply a number of design rules (e.g., rules specifying the minimum line width, minimum line spacing and the like) to produce a mask layout. After the layer design layout is complete, an OPC recipe may be applied to the initial design layout to produce a mask pattern that reproduces the design layout with better fidelity. The OPC recipe adds and/or modifies features in the design layout to compensate for distortion during the lithography step. A checking algorithm may then be applied to determine whether the proposed OPC features properly correct the layer design, so that features patterned using the mask will conform to design and processing requirements for the integrated circuit functionality and manufacturing yield.
Like reference symbols in the various drawings indicate like elements.